The present technology described herein is related to but not limited to nanostructures such as carbon nanostructures (e.g., carbon nanotubes, carbon nanofibers, and carbon nanowires). These nanostructures have gained interest in recent years due to their high thermal and electrical conductivities.
Carbon nanostructures can be manufactured with arc discharge methods, laser ablation, or chemical vapor deposition (CVD). A catalyst is used in CVD processing to obtain growth of the nanostructures. Two most frequently used CVD methods are thermal CVD and plasma-enhanced CVD (i.e., plasma CVD). In thermal CVD, the energy required for formation of the nanostructures is thermal energy. In plasma CVD, the energy required for formation of the nanostructures is from the plasma. Plasma CVD makes it possible to grow nanostructures at a lower temperature than that used in thermal CVD. The lower growth temperature in plasma CVD is a significant advantage as the substrates on which the nanostructures grow are often damaged at excessive temperatures.
Several types of plasma CVD exist, including radio-frequency plasma CVD, inductively-coupled plasma CVD and direct-current plasma CVD. Direct-current plasma CVD (DC-CVD) is often preferred since the electric field close to the substrate surface enables alignment of the growing nanostructures. In some instances, the electric field creates nanostructure alignment that is substantially perpendicular to the substrate. In some instances, alignment with other angular deviation from the perpendicular direction can also be achieved as desired.
FIGS. 1A-1E illustrate various configurations that nanostructures can be grown on a substrate. FIG. 1A illustrates a configuration for growing nanostructures 106 and/or 108 from a patterned catalyst layers 102 and/or 104 on a conducting substrate 100. Nanostructure 106 is a single nanostructure growing on a small catalyst dot 102, while nanostructures 108 is a “forest” of nanostructures (multiple closely-spaced nanostructures) growing on a large catalyst area 104. FIG. 1B illustrates a configuration for growing nanostructures 106 and/or 108 from a patterned catalyst layers 102 and/or 104 on a continuous metal underlayer 112 deposited on a insulating substrate 110. A small catalyst dot 102 gives rise to an individual nanostructure 106, while a large catalyst area 104 gives rise to a “forest” of nanostructures 108 (multiple closely-spaced nanostructures). These two configurations of using DC-CVD to grow nanostructures are relatively straight-forward.
However, problems arise if the patterned catalyst layers 102 and/or 104 are deposited directly on an insulator 110 (as shown in FIG. 1C) or on isolated metal islands 114 over an insulator 110 (as shown in FIG. 1D). The problems will most often occur if there are insulating areas around the metal islands, even if the metal islands are electrically connected to other parts of the substrate. Electric arcs will occur during the growth process, and cause damage to the growth structure due to sputtering. The arcs can also damage the electronic devices connected to the growth structures by the over-voltages produced by the arcs. FIG. 2 shows an example of damage caused on a substrate due to arcing. These over-voltages can damage the devices even if the devices are buried below several material layers, as the devices are electrically connected to the topmost metal layers. U.S. Pat. No. 5,651,865 provides a detailed description of the problems related to having insulating regions on an otherwise conducting surface in a DC plasma.
There are some proposed solutions describing improvements of the DC power supply to reduce the problems with arcs. For example, U.S. Pat. Nos. 5,576,939 and 6,943,317 disclose methods for shutting down or reversing the polarity of the power supply at the onset of an arc. U.S. Pat. No. 5,584,972 describes connecting an inductor and a diode between the power supply and the electrodes. U.S. Pat. No. 7,026,174 discloses putting the wafer at a bias voltage in order to reduce arcing. U.S. Pat. No. 5,651,865 discloses using a periodic polarity change of the plasma voltage to preferentially sputter away any insulator from an otherwise conductive surface, which does not enable the nanostructure growth on samples with insulating regions.
Methods for manufacturing nanofibers on a patterned metal underlayer have been shown for some applications in, for example, U.S. Pat. No. 6,982,519. The methods disclosed consist of growing the nanofibers on a continuous metal underlayer using a patterned catalyst layer, and afterwards patterning the metal underlayer using optical lithography. The disclosed method requires a continuous metal underlayer for the growth, and the patterning of the metal underlayer is made afterwards.
This technique disclosed in U.S. Pat. No. 6,982,519 is not compatible with standard (CMOS) processing of interconnect layers in integrated circuits, where the horizontal metal conductors 116 (e.g., in FIG. 1E) are formed in recesses in the interlayer dielectric using chemical mechanical polishing. After polishing, the next layers of vias (vertical interconnects) is formed on top and next to the interconnect layer. Thus any patterning of interconnects (to obtain patterned metal underlayers) should be done before the manufacturing of the next layer of vias.
With the methods disclosed in U.S. Pat. No. 6,982,519, it is not possible to grow nanostructures directly on an insulating substrate such that the substrate will remain insulating, as there will be metal remaining in between the nanostructures after lithography. In some applications, it is desirable to have the nanostructure-covered surface insulating (e.g., growing nanostructures on the insulating surface 110 in FIG. 1C), for example, in heat transport from insulators (where a continuous metal layer is unwanted).
Furthermore, it is inconvenient to grow nanostructures on existing metal islands (such as that shown in FIG. 1D), and the problem is exemplified by the plasma-induced chip damage as shown in the SEM picture in FIG. 2.
The configuration shown in FIG. 1E includes vias 118 (vertical interconnects) to some underlying (or overlying depending on the way the device is oriented) patterned metal underlayer 116. It would be preferable to grow nanostructures directly on the patterned metal underlayer 116 (horizontal interconnects) or any existing traditional-type vias 118 (vertical interconnects).
Another problem not addressed by U.S. Pat. No. 6,982,519 is that not all metals used in the manufacturing of integrated circuits are compatible with the plasma gases used for growth of nanostructures. For example, U.S. Application Publication No. 2008/00014443 states that it is not possible to use copper in an acetylene-containing plasma as there will be a detrimental chemical reaction.
U.S. Application Publication No. 2007/0154623 discloses a method for using a buffer layer between a glass substrate and the catalyst to prevent interaction. U.S. Application Publication No. 2007/0259128 discloses a method for using an interlayer to control the site density of carbon nanotubes. Neither of these applications fulfills the need for nanostructure growth on already patterned metal underlayers, or for arc elimination.
When growing nanostructures on a chip only partially covered by a metal underlayer, there is sometimes a parasitic growth outside the catalyst particles. This can cause unwanted leakage currents along the chip surface.
Therefore, there is a need of a method to grow the nanostructures on a previously patterned metal underlayer without having the problems of arc-induced chip damage and overvoltage damage of sensitive electronic devices, or problems due to incompatibility of materials used, parasitic growth during plasma growth processing. In various implementations, the technology described herein can solve some or all of these processing-related problems.
The discussion of the background to the invention herein is included to explain the context of the invention. This is not to be taken as an admission that all materials referred to was published, known, or part of the common general knowledge as at the priority date of any of the claims.